Among conventional semiconductor storage devices, a nonvolatile semiconductor storage device having a cell transistor, such as that shown in FIG. 6, is known as a nonvolatile semiconductor storage device for storing multiple bits of information in one cell (prior art 1). A nonvolatile semiconductor storage device according to prior art 1 comprises two first-conductive-type, strip-shaped regions 123a and 123b formed on the surface layer of a semiconductor substrate 121 across a second-conductive-type, strip-shaped semiconductor layer 124a; a first floating gate 127a extending from one of the first-conductive-type regions 123a to one of the sides of the semiconductor layer 124a via an insulator film 122a; a second floating gate 127b extending from the other of the first-conductive-type regions 123b to the other of the sides of the semiconductor layer 124a via an insulator film 122b; and a control gate 130a formed on the top surface of the semiconductor layer 124a via an insulator film 128 (see Patent Document 1). The nonvolatile semiconductor storage device according to prior art 1 has a reliable structure, maintains the localization of trapped charges even if an excessive amount of data is written, and reduces the variation in threshold voltages. In addition, the structure, in which the floating gates 127a and 127b are laid on the regions 123a and 123b of the first conductive type respectively, makes size-reduction possible.
A nonvolatile semiconductor device such as the one shown in FIG. 7 and FIG. 8 is known as one of conventional semiconductor storage devices (prior art 2). A nonvolatile semiconductor storage device according to prior art 2, used in a memory cell, comprises a first diffused region 207a and a second diffused region 207b spaced in parallel on the surface of a substrate 201; a select gate 203 provided on the substrate 201 in the region between the first diffused region 207a and the second diffused region 207b via an insulator film 202; and a third diffused region (221 in FIG. 7) provided on the surface of the substrate 201 and under the select gate 203 outside the cell region and extending in the direction intersecting the select gate 203. In a first region between the first diffused region 207a and the select gate 203 and a second region between the second diffused region 207b and the select gate 203, the nonvolatile semiconductor storage device further comprises a floating gate 206 provided via the insulator film 202; and a control gate 211 provided on the floating gate 206 and the select gate 203 via an insulator film 208. The first diffused region 207a, the floating gate 206, the control gate 211, and the select gate 203 configure a first unit cell, and the second diffused region 207b, the floating gate 206, the control gate 211, and the select gate 203 configure a second unit cell. The select gate 203 has a pair of SG0 and SG1 in one erase block 223 (see FIG. 9). When viewed from the direction of the normal line to the plane, each of SG0 and SG1 has a comb-like shape with the comb teeth of SG0 arranged in the gaps between the comb teeth of SG1 at a predetermined spacing. SG0 and SG1 are electrically connected to all unit cells in the erase block 223. The erase block, composed of multiple unit cells, is a block composed of all unit cells from which electrons are extracted from the floating gate 206 at the same time when the erase operation is performed (the erase operation will be described later). SG0 is electrically connected to a select gate driving circuit 222a, and SG1 is electrically connected to a select gate driving circuit 222b. In the nonvolatile semiconductor storage device according to prior art 2, a positive voltage is applied to the select gate 203 to form an inversion layer 220 on the surface of the substrate 201 below the select gate 203 in the cell region. The nonvolatile semiconductor storage device according to art 2 differs from the nonvolatile semiconductor storage device according to prior art 1 in that (1) there is the select gate 203, (2) the inversion layer 220 is formed below the select gate 203 in the cell region when a positive voltage is applied to the select gate 203, (3) and the region below the floating gate 206 is used as a channel.
The following describes the operation of the nonvolatile semiconductor storage device according to prior art 2 with reference to the drawings. FIG. 10 is a schematic diagram showing the read operation (read operation when electrons are not accumulated in the floating gate) of the semiconductor storage device according to prior art 2. FIG. 11 is a schematic diagram showing the erase operation of the semiconductor storage device according to prior art 2.
Referring to FIG. 10, when electrons are not accumulated in the floating gate 206 (erase state: low threshold voltage) during the read operation, applying a positive voltage to the control gate 211, the select gate 203, and the third diffused region (221 in FIG. 7) causes electrons e in the second diffused region 207b to flow through the channel immediately below the floating gate 206 and through the inversion layer 220 formed below the select gate 203 and to move into the third diffused region (221 in FIG. 7). On the other hand, when electrons are accumulated in the floating gate 206 (write state: high threshold voltage), electrons e do not flow even if a positive voltage is applied to the control gate 211, the select gate 203, and the third diffused region (221 in FIG. 7) because there is no channel below the floating gate 206 (not shown). The read operation is performed by determining the data (0/1) indicating whether or not electrons e flow.
Referring to FIG. 11, applying a negative high voltage to all control gates 211 running through the erase block (223 in FIG. 9) and applying a positive high voltage to the substrate 201 during the erase operation cause the electrons e to be extracted from the floating gate 206 into the substrate 201 via an insulator film 205 (tunnel oxide film) below the floating gate 206 and, as a result, all unit cells in the erase block are erased. Although not shown, it is also possible that data is erased by applying a negative high voltage to the control gate 211 and by applying a positive voltage to the select gate 203 to extract the electrons e from the floating gate 206 into the select gate 203 via the tunnel oxide film 205 on the wall of the floating gate 206.
As compared with the nonvolatile semiconductor storage device according to prior art 1, the nonvolatile semiconductor storage device according to prior art 2 has a configuration in which data is read with the channel of the select gate 203 as the drain. In this configuration, data is read from a target storage node of a first independent unit cell, which is opposed to a non-target storage node across the select gate 203, not via the non-target storage node of a second unit cell. The nonvolatile semiconductor storage device with this configuration, which functions virtually as one bit cell, is advantageous in providing a reliable circuit operation.
[Patent Document 1]
Japanese Patent No. 3249811